URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 65

Rev	Log message	Author	Age	Path
65	Added correct register signals	jlechner	6386d 22h	/
64	* empty log message *	jlechner	6386d 22h	/
63	- Added missing signal stall_out_int to sensitivity list. - LR register now locked if opcode is JUMP.	cwalter	6387d 00h	/
62	no message	cwalter	6387d 02h	/
61	- Applied indenting tool. - Added first basic implementation for testing.	cwalter	6387d 02h	/
60	- Applied indenting tool.	cwalter	6387d 02h	/
59	- We don't want to lock registers the next cycle when we have stalled the previous stages. - Load opcodes also need to lock registers.	cwalter	6387d 02h	/
58	- lr_enable signal in component wb_state should have direction out.	cwalter	6387d 03h	/
57	- applied indenting tool.	cwalter	6387d 04h	/
56	new sensitivity list	ustadler	6387d 04h	/
55	- clear_out must be initialized to '0'.	cwalter	6387d 05h	/
54	- Changed reset delay.	cwalter	6387d 05h	/
53	- Removed unused constant COND_NONE.	cwalter	6387d 05h	/
52	- stall_out must be initialized to '0'	cwalter	6387d 05h	/
51	- stall_out logic has moved to synchronous process.	cwalter	6387d 05h	/
50	- Added assembler example. - Added logic for stall_in. pc_next must not be updated on stall.	cwalter	6387d 05h	/
49	data can be ead asynchronous, data is written with the rising edge of the clk	ustadler	6387d 06h	/
48	- Added ModelSim files.	cwalter	6387d 08h	/
47	- Added GNU assembler patch.	cwalter	6387d 08h	/
46	- Added constant for RESET_VECTOR.	cwalter	6387d 10h	/