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69 Synthesis package containing opcode and conditional constants used in other vhd files.
Package also contains convert functions from std_logic_vector to the appropriate data type.
jlechner 6387d 01h /
68 Simulation package containing enumeration types for opcodes and condition codes.
Package also contains convert functions from std_logic_vector to the appropriate enumeration type.
jlechner 6387d 01h /
67 - Added assembler file. cwalter 6387d 01h /
66 Moved constants for opcode and conditionals in seperate package. jlechner 6387d 01h /
65 Added correct register signals jlechner 6387d 01h /
64 *** empty log message *** jlechner 6387d 01h /
63 - Added missing signal stall_out_int to sensitivity list.
- LR register now locked if opcode is JUMP.
cwalter 6387d 03h /
62 no message cwalter 6387d 05h /
61 - Applied indenting tool.
- Added first basic implementation for testing.
cwalter 6387d 05h /
60 - Applied indenting tool. cwalter 6387d 05h /
59 - We don't want to lock registers the next cycle when we have stalled
the previous stages.
- Load opcodes also need to lock registers.
cwalter 6387d 05h /
58 - lr_enable signal in component wb_state should have direction out. cwalter 6387d 06h /
57 - applied indenting tool. cwalter 6387d 07h /
56 new sensitivity list ustadler 6387d 07h /
55 - clear_out must be initialized to '0'. cwalter 6387d 08h /
54 - Changed reset delay. cwalter 6387d 08h /
53 - Removed unused constant COND_NONE. cwalter 6387d 08h /
52 - stall_out must be initialized to '0' cwalter 6387d 08h /
51 - stall_out logic has moved to synchronous process. cwalter 6387d 08h /
50 - Added assembler example.
- Added logic for stall_in. pc_next must not be updated on stall.
cwalter 6387d 08h /

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