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Rev Log message Author Age Path
12 Updated news of uart.vhd commit. akram.mashni 4885d 22h /
11 Moved debouncer to a new process.
Fixed rx_clk_en generation.
Fixed start of reception condition on rx FSM.
akram.mashni 4885d 22h /
10 Implemented asynchronous mode and RX clock regeneration.
NOT TESTED !!!
akram.mashni 4893d 16h /
9 Updated change log. akram.mashni 4931d 07h /
8 Added Recommended Tools akram.mashni 4931d 07h /
7 Implemented PARITY (not tested!). akram.mashni 4932d 18h /
6 Fixed/improved header.
Changed SPACEs to TABs.
akram.mashni 4933d 23h /
5 Added comments to port map. akram.mashni 4941d 03h /
4 Added "Change Log".
Added "About"
akram.mashni 4941d 04h /
3 Added main file.
Fisrt commit.
Tested in the following conditions:
- Baud rate: 9600 bps.
- Implementation: Xilinx Spartan3e500 (Nexys2 Kit - Digilent)
- Main clock 50 MHz
akram.mashni 4941d 04h /
2 Initial Commit luciorp 4997d 17h /
1 The project and the structure was created root 5025d 14h /

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