URL https://opencores.org/ocsvn/rs232_with_buffer_and_wb/rs232_with_buffer_and_wb/trunk

Subversion Repositories rs232_with_buffer_and_wb

[/] - Rev 14

Rev	Log message	Author	Age	Path
14	Seemt to work witho out errors	TobiasJ	4256d 22h	/
13	Fixed a error in enable_register, which made it possible to commense a transmittion and provide wrong timing at will	TobiasJ	4256d 22h	/
12	Updated "stupid" test benches for the transmitter and reciever funciton	TobiasJ	4257d 21h	/
11	Logic and register is seperated hard. It is messy right now, but hope i can make it look better, exspecially the gathering of the final word is messy	TobiasJ	4257d 21h	/
10	The status of the project so far	TobiasJ	4258d 22h	/
9	Primilary tests shows it is working. The issue with the second and following starts bit being to short has been solved. no new issues has been found	TobiasJ	4258d 23h	/
8	Test benches for rx/tx and buffer	TobiasJ	4258d 23h	/
7	Buffer management for reciever and transmitter	TobiasJ	4259d 00h	/
6	Reciving part of the rs232 part	TobiasJ	4259d 00h	/
5	Triede to clearly seperate combinational logic with register logic, to have more control. Problem after first word is transmitted, the counter counts one to many going into idle mode, therby reducing the count for the secound and following start bits	TobiasJ	4259d 00h	/
4	Testing SVN and SVN program	TobiasJ	4259d 01h	/
3	The transmission part of the project	TobiasJ	4259d 01h	/
2	Project description, messy right now	TobiasJ	4259d 01h	/
1	The project and the structure was created	root	4260d 20h	/