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Subversion Repositories rs232_with_buffer_and_wb

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Rev Log message Author Age Path
16 Should work TobiasJ 4217d 02h /
15 Will test all possible transmitt data, has not been made to cope with paryti and stop bit difference yet, nor has the parity_error or stop_bit_error been exercised TobiasJ 4221d 06h /
14 Seemt to work witho out errors TobiasJ 4221d 06h /
13 Fixed a error in enable_register, which made it possible to commense a transmittion and provide wrong timing at will TobiasJ 4221d 06h /
12 Updated "stupid" test benches for the transmitter and reciever funciton TobiasJ 4222d 04h /
11 Logic and register is seperated hard. It is messy right now, but hope i can make it look better, exspecially the gathering of the final word is messy TobiasJ 4222d 04h /
10 The status of the project so far TobiasJ 4223d 06h /
9 Primilary tests shows it is working. The issue with the second and following starts bit being to short has been solved. no new issues has been found TobiasJ 4223d 06h /
8 Test benches for rx/tx and buffer TobiasJ 4223d 07h /
7 Buffer management for reciever and transmitter TobiasJ 4223d 08h /
6 Reciving part of the rs232 part TobiasJ 4223d 08h /
5 Triede to clearly seperate combinational logic with register logic, to have more control.
Problem after first word is transmitted, the counter counts one to many going into idle mode, therby reducing the count for the secound and following start bits		 TobiasJ 4223d 08h /
4 Testing SVN and SVN program TobiasJ 4223d 08h /
3 The transmission part of the project TobiasJ 4223d 08h /
2 Project description, messy right now TobiasJ 4223d 08h /
1 The project and the structure was created root 4225d 04h /

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