URL https://opencores.org/ocsvn/rs232_with_buffer_and_wb/rs232_with_buffer_and_wb/trunk

Subversion Repositories rs232_with_buffer_and_wb

[/] - Rev 26

Rev	Log message	Author	Age	Path
26	Works	TobiasJ	4382d 09h	/
25	Uart_top, top entitu of the uart, with all components inside it	TobiasJ	4382d 09h	/
24		TobiasJ	4383d 21h	/
23		TobiasJ	4383d 21h	/
22	name change and creation	TobiasJ	4384d 08h	/
21	name change	TobiasJ	4384d 08h	/
20	created file	TobiasJ	4384d 08h	/
19	renamed the file	TobiasJ	4384d 08h	/
18	renamed the file	TobiasJ	4384d 08h	/
17	tests the tx fifo	TobiasJ	4384d 23h	/
16	Should work	TobiasJ	4384d 23h	/
15	Will test all possible transmitt data, has not been made to cope with paryti and stop bit difference yet, nor has the parity_error or stop_bit_error been exercised	TobiasJ	4389d 02h	/
14	Seemt to work witho out errors	TobiasJ	4389d 02h	/
13	Fixed a error in enable_register, which made it possible to commense a transmittion and provide wrong timing at will	TobiasJ	4389d 02h	/
12	Updated "stupid" test benches for the transmitter and reciever funciton	TobiasJ	4390d 00h	/
11	Logic and register is seperated hard. It is messy right now, but hope i can make it look better, exspecially the gathering of the final word is messy	TobiasJ	4390d 00h	/
10	The status of the project so far	TobiasJ	4391d 02h	/
9	Primilary tests shows it is working. The issue with the second and following starts bit being to short has been solved. no new issues has been found	TobiasJ	4391d 03h	/
8	Test benches for rx/tx and buffer	TobiasJ	4391d 03h	/
7	Buffer management for reciever and transmitter	TobiasJ	4391d 04h	/