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URL https://opencores.org/ocsvn/rv01_riscv_core/rv01_riscv_core/trunk

Subversion Repositories rv01_riscv_core

[/] - Rev 5

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Rev Log message Author Age Path
5 First release is complete. madsilicon 2531d 08h /
4 madsilicon 2532d 05h /
3 madsilicon 2532d 05h /
2 Added core documentation, self-test simulation script for Modelsim and VHDL source files. madsilicon 2536d 08h /
1 The project and the structure was created root 2538d 21h /

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