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Rev Log message Author Age Path
102 This version correctly initializes the SPARC Core and then jumps at address 0x144000 on Bank 0. fafa1971 5821d 07h /
101 Should assign all the 4 bits of completion signal the same value. fafa1971 5825d 13h /
100 SPU removed by hand. fafa1971 5825d 13h /
99 This bridge follows the rules stated in paragraph 6.8 of book "OpenSPARC Internals"
in order to stall all the threads while serving a single request.		 fafa1971 5826d 06h /
98 Added stall/resume signals from bridge to SPARC Core. fafa1971 5826d 07h /
97 Changed hack to insert stall signal into the core (following OpenSPARC Internals book) fafa1971 5826d 07h /
96 File lists with updated SPARC Core code. fafa1971 5841d 12h /
95 Files from OpenSPARCT1.1.6 with the SPU instance removed from the sparc.v top-level. fafa1971 5841d 12h /
94 Removed files with dependencies from the SPU. fafa1971 5841d 12h /
93 Now uses a local version of sparc.v with SPU instance removed by hand. fafa1971 5841d 12h /
92 Added top-level of SPARC Core with SPU section removed (will be copied by update_sparccore). fafa1971 5841d 12h /
91 Filelists updated according to preprocessed files from OpenSPARC T1 1.6 fafa1971 5945d 06h /
90 Added newer files from OpenSPARC T1 1.6 preprocessed with "update_sparccore -ee" fafa1971 5945d 06h /
89 Removed files originated from OpenSPARC T1 Design 1.5 preprocessed with "update_sparccore -me" fafa1971 5945d 06h /
88 After one year found time to translate Giovanni Di Blasi's comments to boot code! fafa1971 5947d 08h /
87 Corrected comment delimiter. fafa1971 6073d 18h /
86 Added 'lain.ux'-style checks for environment vars to be set (I lost data as well!!!). fafa1971 6086d 13h /
85 GREAT synthesis script!!! Performs all bottom-up synthesis without errors. fafa1971 6088d 15h /
84 Again, used module names instead than instance names in bottom-up synthesis approach. fafa1971 6088d 17h /
83 Decreased clock frequency from 250 to 200 MHz. fafa1971 6095d 13h /

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