OpenCores
URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] - Rev 54

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
54 Updated filelists fafa1971 6271d 13h /
53 Removed from CVS tree because header file preprocessing is done elsewhere fafa1971 6271d 13h /
52 Updated SPARC Core files from OpenSPARC T1 version 1.4 to version 1.5 fafa1971 6271d 13h /
51 User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables. fafa1971 6357d 13h /
50 Changed library paths for XST from macrocell to behav. fafa1971 6373d 20h /
49 Now supports 3 versions: S1 Core ME/SE/EE. fafa1971 6380d 21h /
48 Updated with new OpenSPARC 1.4 list fafa1971 6422d 12h /
47 Updated with `define preprocessing for Xilinx XST synthesis fafa1971 6422d 12h /
46 Fresh version from OpenSPARC 1.4 and Icarus define preprocessing fafa1971 6422d 12h /
45 I'm going to remove original OpenSPARC 1.4 files so that I can insert again
the ones with Icarus Verilog preprocessor already applied by update_sparccore
(it seems that Xilinx's XST does NOT support defines at compile time)		 fafa1971 6422d 12h /
44 Embedded `defines into Verilog source since did not find command line option for XST fafa1971 6423d 10h /
43 Added welcome message as a remainder to set paths for tools!=IVerilog fafa1971 6423d 10h /
42 Added support for filelist for Xilinx ISE XST synthesis fafa1971 6423d 10h /
41 Added copy of empty modules upon original SPARC copies fafa1971 6423d 10h /
40 First version of synthesis script for Xilinx ISE XST fafa1971 6423d 10h /
39 Empty modules for cacheless Simply RISC S1 Core fafa1971 6423d 10h /
38 Changed to compile (for now) the boot code. fafa1971 6427d 09h /
37 Memory image coming from the new boot.s fafa1971 6427d 09h /
36 Working boot code!!! fafa1971 6427d 09h /
35 Fixed Assembly comments ("//" had to become "!!"). fafa1971 6427d 10h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.