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Rev	Log message	Author	Age	Path
64	Initial version B C C Initial versioNCVS: ----------------------------------------------------------------------	fafa1971	6229d 08h	/
63	* empty log message *	fafa1971	6229d 08h	/
62	Documentation files updated to reflect the 3 different flavors of S1 Core	fafa1971	6275d 07h	/
61	Updated to latest version	fafa1971	6275d 07h	/
60	Now supports also Virtex5 devices	fafa1971	6275d 07h	/
59	Now it is just one line	fafa1971	6275d 07h	/
58	These were only symbolic links to remember where such these things were defined	fafa1971	6275d 07h	/
57	Latest version	fafa1971	6275d 07h	/
56	Updated from OpenSPARC T1 version 1.4 to version 1.5	fafa1971	6275d 07h	/
55	Nobody remembers why these blackboxed files were required!	fafa1971	6275d 07h	/
54	Updated filelists	fafa1971	6275d 07h	/
53	Removed from CVS tree because header file preprocessing is done elsewhere	fafa1971	6275d 07h	/
52	Updated SPARC Core files from OpenSPARC T1 version 1.4 to version 1.5	fafa1971	6275d 07h	/
51	User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables.	fafa1971	6361d 07h	/
50	Changed library paths for XST from macrocell to behav.	fafa1971	6377d 14h	/
49	Now supports 3 versions: S1 Core ME/SE/EE.	fafa1971	6384d 15h	/
48	Updated with new OpenSPARC 1.4 list	fafa1971	6426d 06h	/
47	Updated with `define preprocessing for Xilinx XST synthesis	fafa1971	6426d 06h	/
46	Fresh version from OpenSPARC 1.4 and Icarus define preprocessing	fafa1971	6426d 06h	/
45	I'm going to remove original OpenSPARC 1.4 files so that I can insert again the ones with Icarus Verilog preprocessor already applied by update_sparccore (it seems that Xilinx's XST does NOT support defines at compile time)	fafa1971	6426d 06h	/

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[/] - Rev 64

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