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Rev Log message Author Age Path
85 GREAT synthesis script!!! Performs all bottom-up synthesis without errors. fafa1971 5948d 13h /
84 Again, used module names instead than instance names in bottom-up synthesis approach. fafa1971 5948d 16h /
83 Decreased clock frequency from 250 to 200 MHz. fafa1971 5955d 11h /
82 DC synthesis script modified according to the fabolous manual (RTFM...). fafa1971 5966d 11h /
81 Sorry, I made a mistake in the waveform of the clock! fafa1971 5966d 15h /
80 Hyerarchical report_area. fafa1971 5969d 11h /
79 Relaxed timing, added flatten and hyerarchical report_area. fafa1971 5969d 11h /
78 Relaxed timing and added flatten command. fafa1971 5969d 11h /
77 Now includes comments (in Italian!) fafa1971 6054d 09h /
76 Changed again from DB export to DDC export fafa1971 6069d 08h /
75 Changed preprocessing for DC synthesis fafa1971 6069d 12h /
74 Updated filelists. fafa1971 6069d 12h /
73 New version of scripts for DC and to compile boot code fafa1971 6069d 13h /
72 Modified RAM address from 0x400C0 to 0x4C000 fafa1971 6075d 19h /
71 Added check for S1_ROOT set (suggested by lain.ux) fafa1971 6076d 19h /
70 Again, the setup file is linked rather than copied fafa1971 6084d 05h /
69 Now contains also the other file fafa1971 6084d 05h /
68 Merged with the DC setup file fafa1971 6084d 05h /
67 Now uses XG/Tcl syntax fafa1971 6086d 05h /
66 Modified to use XG syntax fafa1971 6086d 05h /

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