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Rev Log message Author Age Path
99 This bridge follows the rules stated in paragraph 6.8 of book "OpenSPARC Internals"
in order to stall all the threads while serving a single request.		 fafa1971 5792d 11h /
98 Added stall/resume signals from bridge to SPARC Core. fafa1971 5792d 11h /
97 Changed hack to insert stall signal into the core (following OpenSPARC Internals book) fafa1971 5792d 11h /
96 File lists with updated SPARC Core code. fafa1971 5807d 17h /
95 Files from OpenSPARCT1.1.6 with the SPU instance removed from the sparc.v top-level. fafa1971 5807d 17h /
94 Removed files with dependencies from the SPU. fafa1971 5807d 17h /
93 Now uses a local version of sparc.v with SPU instance removed by hand. fafa1971 5807d 17h /
92 Added top-level of SPARC Core with SPU section removed (will be copied by update_sparccore). fafa1971 5807d 17h /
91 Filelists updated according to preprocessed files from OpenSPARC T1 1.6 fafa1971 5911d 11h /
90 Added newer files from OpenSPARC T1 1.6 preprocessed with "update_sparccore -ee" fafa1971 5911d 11h /
89 Removed files originated from OpenSPARC T1 Design 1.5 preprocessed with "update_sparccore -me" fafa1971 5911d 11h /
88 After one year found time to translate Giovanni Di Blasi's comments to boot code! fafa1971 5913d 13h /
87 Corrected comment delimiter. fafa1971 6039d 22h /
86 Added 'lain.ux'-style checks for environment vars to be set (I lost data as well!!!). fafa1971 6052d 18h /
85 GREAT synthesis script!!! Performs all bottom-up synthesis without errors. fafa1971 6054d 19h /
84 Again, used module names instead than instance names in bottom-up synthesis approach. fafa1971 6054d 22h /
83 Decreased clock frequency from 250 to 200 MHz. fafa1971 6061d 18h /
82 DC synthesis script modified according to the fabolous manual (RTFM...). fafa1971 6072d 18h /
81 Sorry, I made a mistake in the waveform of the clock! fafa1971 6072d 21h /
80 Hyerarchical report_area. fafa1971 6075d 17h /

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