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9 Added pinout diagrams, based upon a (hopefully) final UCF file. dgisselq 3269d 09h /
8 First pseudo-running version. The alternate configuration (not the main one)
has been initially tested. wbregs works for reading/writing registers,
so it is now possible to test the peripherals.
dgisselq 3274d 09h /
7 Created/added an initial specification. Updated/corrected several copywrite
notices.
dgisselq 3275d 00h /
6 Initial UCF modifications. Pin layout still isn't complete, but I'm starting
to work it.
dgisselq 3295d 19h /
5 These two are my first attempt(s) at a secondary project file, one that can
run as an alternate to the main file but that gives more access to the hardware,
such as programming access to the flash.
dgisselq 3295d 19h /
4 Lots of updates, as part of actually making this work on hardware. Not there
yet, so this is still pre-alpha.
dgisselq 3295d 19h /
3 Updated date. dgisselq 3295d 19h /
2 The initial check in--all the files that will make this SoC work. dgisselq 3306d 14h /
1 The project and the structure was created root 3306d 16h /

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