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Rev Log message Author Age Path
109 Added a data ram. rkastl 5076d 20h /
108 Added a ram to the testbed rkastl 5076d 20h /
107 Forgot to add Counter in last commit. rkastl 5076d 20h /
106 Fixes #29: All cards respond, but they do not all work. rkastl 5076d 20h /
105 Changing speed works! refs #33 rkastl 5076d 20h /
104 SdController: Configuration ready to switch to high speed, refs #33 rkastl 5076d 20h /
103 SdController: Checking speed works rkastl 5076d 20h /
102 SdController: Enabling wide mode works, refs #33 rkastl 5076d 20h /
101 Receiving response to ACMD51 works including data, refs #33. rkastl 5076d 20h /
100 SdController: Receiving data after ACMD51, but CRC is wrong rkastl 5076d 20h /
99 SdController: Checking bus width without receiving data response rkastl 5076d 20h /
98 SdController: Receive response to CMD7 (except when busy is activated) rkastl 5076d 20h /
97 SdController: CMD55 out of main state into Region rkastl 5076d 20h /
96 SdController: Region extracted from main state, select card in config
state		 rkastl 5076d 20h /
95 SdController: entity and architecture split, all outputs registered
SdCardModel: Delay between response and next command added
SdData: Busy checking

refs #33		 rkastl 5076d 20h /
94 CmdTimeout (8 Clocks) added, SdData inserted into top, refs #31 rkastl 5076d 20h /
93 Don´t run a full synthesis for SdData alone. It won´t fit. rkastl 5076d 20h /
92 SdData: Sending in standard and wide mode (incl. simple not automated
testbench and synthesis), refs #31.		 rkastl 5076d 20h /
91 Settings for tty. rkastl 5076d 20h /
90 Fixes the milestone ReadCID. It works with SD2.0 (non HC) card. rkastl 5076d 20h /

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