URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] - Rev 133

Rev	Log message	Author	Age	Path
133	SdData: Further refactoring	rkastl	5090d 07h	/
132	SdData: Refactoring, not done. Testbench works again, but does not really test anything.	rkastl	5090d 07h	/
131	SdClockMaster added to regression tests	rkastl	5090d 07h	/
130	SdClockMaster: Formal verification	rkastl	5090d 07h	/
129	SdClockMaster: Redesigned, not finished. Tb with PSL assertions.	rkastl	5090d 07h	/
128	Sim: Support for psl files added.	rkastl	5090d 07h	/
127	Thesis: Restructured SDHC chapter.	rkastl	5090d 07h	/
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	5090d 07h	/
125	Write works in simulation	rkastl	5090d 07h	/
124	Write: SdClk is disabled, if no data is available.	rkastl	5090d 07h	/
123	Write: Must be able to halt SdClk, rest is done.	rkastl	5090d 07h	/
122	SdController: Initial read support	rkastl	5090d 11h	/
121	SdWbSlave inserted into SdTop. SdController does not use it yet.	rkastl	5090d 11h	/
120	SdWbSlave: ClassicRead and ClassicWrite work	rkastl	5090d 11h	/
119	SdWb: Synchronization of operation to SdController done, but needs testing.	rkastl	5090d 11h	/
118	EdgeDetector added.	rkastl	5090d 11h	/
117	Removed unused units.	rkastl	5090d 11h	/
116	Wishbone interface for sd core started	rkastl	5090d 11h	/
115	WbSlave: New header.	rkastl	5090d 11h	/
114	Read works with model too.	rkastl	5090d 11h	/