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Rev Log message Author Age Path
149 SdBFM:
+ mailbox mode
rkastl 5062d 21h /
148 SdVerification:
+ CardModel: Execution thread which starts initialization and
then receives token and parses them.

TbdSd:
+ Added SdWbSdSynchronization.
rkastl 5062d 21h /
147 Sd-Core:
+ Added checking of Busy signal after write
rkastl 5062d 21h /
146 SdClockMaster:
+ fixed output of data at negedge of sclk in high speed mode
rkastl 5062d 21h /
145 Verification:
+ SdCardModel and SdBFM seperated
rkastl 5062d 21h /
144 Simulation files for tbTbdSd created.

tbTbdSd is not done and TestWbMaster seems to be lost.
rkastl 5062d 21h /
143 Ignore pattern:
+ work
+ modelsim.ini
+ vsim.wlf
+ transcript
+ cycloneii and altera_mf generated library folders
rkastl 5062d 21h /
142 Thesis: PDF added to .gitignore rkastl 5062d 21h /
141 Added *.bak to ignore file. rkastl 5062d 21h /
140 Removed tbSdData-Bhv-ea.vhdl. Non-automated tb, tested in complete
verification tb anyway.
rkastl 5062d 21h /
139 Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in
the complete verification environment anyway.
rkastl 5062d 21h /
138 Removed testbench for unitSdCmd because it was a weak testbench and the
functionality is tested in the SdVerificationTestbench anyway.
rkastl 5062d 22h /
137 Regression test suite:

Removed unneeded testbenches from the makefile. Only complete reusable
blocks are tested from now on.
rkastl 5062d 22h /
136 SDHC:
- SdData refactored to use a single counter
- TestWbMaster added to TbdSd (not functional yet)
rkastl 5062d 22h /
135 Multiple-Inclusion-Protection to SystemVerilog files added
Stops using relative paths in `includes. instead +incdir has to be used.
rkastl 5062d 22h /
134 SdData: Further refactoring. rkastl 5062d 22h /
133 SdData: Further refactoring rkastl 5062d 22h /
132 SdData: Refactoring, not done.
Testbench works again, but does not really test anything.
rkastl 5062d 22h /
131 SdClockMaster added to regression tests rkastl 5062d 22h /
130 SdClockMaster: Formal verification rkastl 5062d 22h /

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