URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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Rev	Log message	Author	Age	Path
176	Thesis: Conclusion Fixes #53,#61.	rkastl	4912d 12h	/
175	Thesis: Fixes #45.	rkastl	4912d 13h	/
174	Thesis: System integration Fixes #51.	rkastl	4912d 13h	/
173	Thesis: Started with SdController description. Refs #38.	rkastl	4912d 13h	/
172	Thesis: wbclockdomain: refactored and finished. Fixes #39.	rkastl	4912d 13h	/
171	Worked on wishbone part of thesis. Refs #37. Refs #39.	rkastl	4912d 13h	/
170	License rewritten to BSD	rkastl	4912d 13h	/
169	+sdc file for timing analysis	rkastl	4912d 13h	/
168	TbdSd synthesis script reaches timing constraints.	rkastl	4912d 13h	/
167	Read+Modify+Write works on HW + Fixed CRC status token (not mentioned in simplified spec) + Improved TestWbMaster to RMW	rkastl	4912d 13h	/
166	tbTbdSd: fixed	rkastl	4912d 13h	/
165	Only use synchronous high active reset in SDHC-SC-Core.	rkastl	4912d 13h	/
164	Headers updated (LGPL, consistent format)	rkastl	4912d 13h	/
163	Header-Skript supports writing to file and infile replacement.	rkastl	4912d 13h	/
162	Script for generating headers created.	rkastl	4912d 13h	/
161	Verification: CardModel: Check CRC on received data	rkastl	4912d 13h	/
160	Verification: Full random read and write single blocks sequence works with checks. Checking the CRC in the card model is missing. Writing at addresses above the card size is missing. Erasing is missing.	rkastl	4912d 13h	/
159	Verification: Further work: Checking RAM Actions and reading data is still missing	rkastl	4912d 13h	/
158	Verification: Work on Checking Functional coverage	rkastl	4912d 13h	/
157	Verification: Testcase with Reads works but Verification not completly implemented.	rkastl	4912d 13h	/

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Subversion Repositories sdhc-sc-core

[/] - Rev 176

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