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Rev Log message Author Age Path
31 Makefile: $(quartus) has to be set individually rkastl 4904d 03h /
30 Wishbone: No wave.do rkastl 4904d 03h /
29 Sd: package started rkastl 4904d 03h /
28 Wishbone: reads and writes as procedures in the tb rkastl 4904d 03h /
27 Wishbone: Testbench tests a single ClassicRead rkastl 4904d 03h /
26 Wishbone: Changed entity to reflect the real width of iAdr rkastl 4904d 03h /
25 Wishbone: ClassicRead and ClassicWrite implemented, basic testbench
created
rkastl 4904d 03h /
24 Wishbone: Build fixed for splitted packages. rkastl 4904d 03h /
23 Wishbone: Package split into a global and a specific one. rkastl 4904d 03h /
22 Wishbone: Processes for statemachine created rkastl 4904d 03h /
21 Wishbone: Control signals into records, unfortunately signals with a
width dependend on generics can not be used in records before VHDL2008.
rkastl 4904d 03h /
20 Wishbone: Directions added to port, support for synchronous cycle
termination added to entity (and therefore new types in the package were
created)
rkastl 4904d 03h /
19 Wishbone: Fixed syntax errors in WbSlave-Rtl-ea.vhdl
Only commit after a sucessful compiler run.
rkastl 4904d 03h /
18 Wishbone: Slave entity started, Build file generated rkastl 4904d 03h /
17 Fixed error introduced in last commit. rkastl 4904d 03h /
16 Indenting changed (vim)
added an error to test the ci-system
rkastl 4904d 03h /
15 Support quartus tcl scripts in the Makefiles rkastl 4904d 03h /
14 Moved the Makefiles to root. rkastl 4904d 03h /
13 Made simulation makefiles recursive so all simulations can be started
from a common point.
rkastl 4904d 03h /
12 Headless quartus compile script. rkastl 4904d 03h /

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