URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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Rev	Log message	Author	Age	Path
32	SD: Entity for the top level entity with a SD controller SD: Started on the SdController entity.	rkastl	5067d 05h	/
31	Makefile: $(quartus) has to be set individually	rkastl	5067d 05h	/
30	Wishbone: No wave.do	rkastl	5067d 05h	/
29	Sd: package started	rkastl	5067d 05h	/
28	Wishbone: reads and writes as procedures in the tb	rkastl	5067d 05h	/
27	Wishbone: Testbench tests a single ClassicRead	rkastl	5067d 05h	/
26	Wishbone: Changed entity to reflect the real width of iAdr	rkastl	5067d 05h	/
25	Wishbone: ClassicRead and ClassicWrite implemented, basic testbench created	rkastl	5067d 05h	/
24	Wishbone: Build fixed for splitted packages.	rkastl	5067d 05h	/
23	Wishbone: Package split into a global and a specific one.	rkastl	5067d 05h	/
22	Wishbone: Processes for statemachine created	rkastl	5067d 05h	/
21	Wishbone: Control signals into records, unfortunately signals with a width dependend on generics can not be used in records before VHDL2008.	rkastl	5067d 05h	/
20	Wishbone: Directions added to port, support for synchronous cycle termination added to entity (and therefore new types in the package were created)	rkastl	5067d 05h	/
19	Wishbone: Fixed syntax errors in WbSlave-Rtl-ea.vhdl Only commit after a sucessful compiler run.	rkastl	5067d 05h	/
18	Wishbone: Slave entity started, Build file generated	rkastl	5067d 05h	/
17	Fixed error introduced in last commit.	rkastl	5067d 05h	/
16	Indenting changed (vim) added an error to test the ci-system	rkastl	5067d 05h	/
15	Support quartus tcl scripts in the Makefiles	rkastl	5067d 05h	/
14	Moved the Makefiles to root.	rkastl	5067d 05h	/
13	Made simulation makefiles recursive so all simulations can be started from a common point.	rkastl	5067d 05h	/

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Subversion Repositories sdhc-sc-core

[/] - Rev 32

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