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Rev Log message Author Age Path
13 column bit are made progrmmable dinesha 4570d 23h /
12 Column Bits are made programmable dinesha 4570d 23h /
11 SDRAM Specification document added into SVN dinesha 4573d 23h /
10 Waveform files are added into SVN dinesha 4573d 23h /
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4574d 23h /
8 test bench files are added into SVN dinesha 4574d 23h /
7 SDRAM Memory Models are added into SVN dinesha 4574d 23h /
6 Golden Log files are added into SVN dinesha 4574d 23h /
5 Run files are updated into SVN dinesha 4574d 23h /
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4575d 21h /
3 SDRAM controller core files are checked in dinesha 4582d 07h /
2 dinesha 4584d 23h /
1 The project and the structure was created root 4588d 23h /

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