URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 17

Rev	Log message	Author	Age	Path
17	micron 8 bit memory models are added into svn	dinesha	4691d 18h	/
16	8 Bit SDRAM Support is added	dinesha	4691d 18h	/
15	Port cleanup	dinesha	4694d 19h	/
14	Unnecessary device config are removed	dinesha	4694d 19h	/
13	column bit are made progrmmable	dinesha	4694d 19h	/
12	Column Bits are made programmable	dinesha	4694d 19h	/
11	SDRAM Specification document added into SVN	dinesha	4697d 20h	/
10	Waveform files are added into SVN	dinesha	4697d 20h	/
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4698d 20h	/
8	test bench files are added into SVN	dinesha	4698d 20h	/
7	SDRAM Memory Models are added into SVN	dinesha	4698d 20h	/
6	Golden Log files are added into SVN	dinesha	4698d 20h	/
5	Run files are updated into SVN	dinesha	4698d 20h	/
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4699d 17h	/
3	SDRAM controller core files are checked in	dinesha	4706d 03h	/
2		dinesha	4708d 20h	/
1	The project and the structure was created	root	4712d 19h	/