URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 49

Rev	Log message	Author	Age	Path
49	clean up	dinesha	4675d 09h	/
48	top-level cleanup	dinesha	4675d 09h	/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4675d 09h	/
46	test bench upgrade + rtl cleanup	dinesha	4677d 10h	/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4677d 14h	/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4679d 12h	/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4679d 14h	/
42	Bug fix in read access is fixed	dinesha	4679d 14h	/
41	Updated Spec ver 0.1 is added back to svn	dinesha	4679d 15h	/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4680d 08h	/
39	Test Bench upgradation with bigger data burst size	dinesha	4680d 09h	/
38	Port Name clean up	dinesha	4681d 14h	/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4681d 15h	/
36	Clean up	dinesha	4682d 06h	/
35	Updated the New Documents - ver 0.1	dinesha	4682d 08h	/
34	Removed the older version	dinesha	4682d 08h	/
33	clean up	dinesha	4682d 08h	/
32	Debug is enable through +define	dinesha	4684d 07h	/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4684d 07h	/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4684d 07h	/