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Rev Log message Author Age Path
23 Disable clear signal. arif_endro 5887d 11h /
22 Update last bit output assignment method. arif_endro 5887d 11h /
21 This commit was manufactured by cvs2svn to create tag 'version_1_1'. 7072d 12h /
20 New Version arif_endro 7072d 12h /
19 Screen shot from chipscope analyzer view, this is how this design work. arif_endro 7078d 11h /
18 This bit files generates better wave than previous (i.e. more smooth) arif_endro 7078d 13h /
17 Initial Checkin arif_endro 7086d 10h /
16 Changes constan and minor fix arif_endro 7089d 13h /
15 Xilinx FPGA XC2V2000 bit files the first version. arif_endro 7092d 11h /
14 *** empty log message *** arif_endro 7097d 09h /
13 Update License arif_endro 7108d 10h /
12 Update License
Change reset signal handle
arif_endro 7108d 11h /
11 Update License
Change reset signal handle
arif_endro 7108d 11h /
10 Added script for generating cos ROM. arif_endro 7118d 13h /
9 Added documentation arif_endro 7135d 12h /
8 This commit was manufactured by cvs2svn to create tag 'okinawa_1'. 7149d 13h /
7 To view chipscope exported output using ModelSim waveform window arif_endro 7149d 13h /
6 Added Xilinx FPGA implementation (e.g. connector to ILA, ICON, and VIO) arif_endro 7150d 15h /
5 Added interface in/out and testing paralelly (e.g. square and triangular) arif_endro 7150d 15h /
4 Fix elsif and if statement arif_endro 7153d 08h /

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