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Rev Log message Author Age Path
29 Done fixing Makefile for Alliance. arif_endro 5998d 11h /
28 chip IO place. arif_endro 5999d 06h /
27 chip IO interface. arif_endro 5999d 06h /
26 Removed. arif_endro 5999d 06h /
25 IO place. arif_endro 5999d 06h /
24 Update to use Alliance CAD System by ASIM/LIP6/UMPC arif_endro 5999d 08h /
23 Disable clear signal. arif_endro 5999d 08h /
22 Update last bit output assignment method. arif_endro 5999d 08h /
21 This commit was manufactured by cvs2svn to create tag 'version_1_1'. 7184d 09h /
20 New Version arif_endro 7184d 09h /
19 Screen shot from chipscope analyzer view, this is how this design work. arif_endro 7190d 08h /
18 This bit files generates better wave than previous (i.e. more smooth) arif_endro 7190d 10h /
17 Initial Checkin arif_endro 7198d 07h /
16 Changes constan and minor fix arif_endro 7201d 10h /
15 Xilinx FPGA XC2V2000 bit files the first version. arif_endro 7204d 09h /
14 *** empty log message *** arif_endro 7209d 06h /
13 Update License arif_endro 7220d 08h /
12 Update License
Change reset signal handle
arif_endro 7220d 08h /
11 Update License
Change reset signal handle
arif_endro 7220d 08h /
10 Added script for generating cos ROM. arif_endro 7230d 11h /

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