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Rev Log message Author Age Path
34 Added old uploaded documents to new repository. root 5726d 21h /
33 Added old uploaded documents to new repository. root 5727d 03h /
32 New directory structure. root 5727d 03h /
31 Include flattening process, simplify build system. arif_endro 5939d 03h /
30 Clean up. arif_endro 5983d 08h /
29 Done fixing Makefile for Alliance. arif_endro 5983d 08h /
28 chip IO place. arif_endro 5984d 04h /
27 chip IO interface. arif_endro 5984d 04h /
26 Removed. arif_endro 5984d 04h /
25 IO place. arif_endro 5984d 04h /
24 Update to use Alliance CAD System by ASIM/LIP6/UMPC arif_endro 5984d 06h /
23 Disable clear signal. arif_endro 5984d 06h /
22 Update last bit output assignment method. arif_endro 5984d 06h /
21 This commit was manufactured by cvs2svn to create tag 'version_1_1'. 7169d 07h /
20 New Version arif_endro 7169d 07h /
19 Screen shot from chipscope analyzer view, this is how this design work. arif_endro 7175d 06h /
18 This bit files generates better wave than previous (i.e. more smooth) arif_endro 7175d 08h /
17 Initial Checkin arif_endro 7183d 05h /
16 Changes constan and minor fix arif_endro 7186d 08h /
15 Xilinx FPGA XC2V2000 bit files the first version. arif_endro 7189d 06h /

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