URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

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Rev	Log message	Author	Age	Path
105	moved or1200_monitor from testbench to dut	jt_eaton	4647d 03h	/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4649d 04h	/
103	added user guide resynced to local repository	jt_eaton	4669d 04h	/
102	all ip-xact files now readable by kactus2	jt_eaton	4731d 00h	/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4732d 02h	/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4744d 09h	/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4787d 02h	/
98	removed unneeded sim	jt_eaton	4823d 06h	/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4823d 07h	/
96	hierConnections now create ports	jt_eaton	4897d 03h	/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4906d 01h	/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4933d 02h	/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4945d 14h	/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4950d 15h	/
91	fixed all sims, coverage not working	jt_eaton	4958d 10h	/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4959d 02h	/
89	removed unneeded debug directories	jt_eaton	4980d 11h	/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4980d 11h	/
87	removed prebuilt geda schematics and symbols	jt_eaton	4991d 03h	/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4999d 00h	/

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Subversion Repositories socgen

[/] - Rev 105

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