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Rev Log message Author Age Path
123 added support for ubuntu 12.10 jt_eaton 4369d 17h /
122 Moved Nexys2 from opencores.org to digilentinc.com
Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components
jt_eaton 4377d 20h /
121 cleaned up sims, added autogenerated test bench files
removed mrisc and experimental or1k code
jt_eaton 4398d 02h /
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench
jt_eaton 4416d 02h /
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace
jt_eaton 4450d 20h /
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs
jt_eaton 4486d 05h /
117 added yellow pages tools jt_eaton 4514d 00h /
116 added build_header
now use build_register for all spr components
resynced or1200 code back to use orbuild toolchain
jt_eaton 4548d 21h /
115 split or1200_cpu up into all ip-xact components
removed dead files
jt_eaton 4593d 02h /
114 moved or1200 connectivity out of verilog and into ip-xact
added or1200_boot block
removed force of 00 on lowest iwb_addr bits
jt_eaton 4605d 02h /
113 started refactoring or1200 jt_eaton 4610d 18h /
112 added more test sims
removed unneeded files
jt_eaton 4620d 07h /
111 split or1200 out into seperate test suite jt_eaton 4622d 01h /
110 split out more ip-xact components
added sw sources
jt_eaton 4633d 23h /
109 removed unused file jt_eaton 4636d 22h /
108 removed unneeded files jt_eaton 4638d 05h /
107 added designCfg files to all modules jt_eaton 4638d 07h /
106 checked in orp_soc project step 2 jt_eaton 4644d 00h /
105 moved or1200_monitor from testbench to dut jt_eaton 4646d 21h /
104 fixed search in preprocessor script
added initial orp_soc project
jt_eaton 4648d 21h /

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