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Rev Log message Author Age Path
130 Dec 2014 major release
trimmed out some IP
replaced perl database with Berkeley
jt_eaton 3633d 16h /
129 removed unneeded 6502 files jt_eaton 4088d 22h /
128 major cleanup
added toolflows for sim,syn,documentation,linting and verilog
added documentation tools
jt_eaton 4088d 22h /
127 final cleanup before DAC jt_eaton 4203d 18h /
126 added mor1kx
cleanup
jt_eaton 4256d 23h /
125 Added two new 6502 cores in www.6502.org

cleaned up sogen xml files and added module name control
jt_eaton 4301d 17h /
124 beta release candidate 1
changed design.xml name
aligned schema with filesystem
jt_eaton 4354d 20h /
123 added support for ubuntu 12.10 jt_eaton 4369d 12h /
122 Moved Nexys2 from opencores.org to digilentinc.com
Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components
jt_eaton 4377d 15h /
121 cleaned up sims, added autogenerated test bench files
removed mrisc and experimental or1k code
jt_eaton 4397d 21h /
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench
jt_eaton 4415d 21h /
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace
jt_eaton 4450d 16h /
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs
jt_eaton 4486d 01h /
117 added yellow pages tools jt_eaton 4513d 20h /
116 added build_header
now use build_register for all spr components
resynced or1200 code back to use orbuild toolchain
jt_eaton 4548d 17h /
115 split or1200_cpu up into all ip-xact components
removed dead files
jt_eaton 4592d 21h /
114 moved or1200 connectivity out of verilog and into ip-xact
added or1200_boot block
removed force of 00 on lowest iwb_addr bits
jt_eaton 4604d 21h /
113 started refactoring or1200 jt_eaton 4610d 13h /
112 added more test sims
removed unneeded files
jt_eaton 4620d 02h /
111 split or1200 out into seperate test suite jt_eaton 4621d 21h /

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