URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 20

Rev	Log message	Author	Age	Path
20	added Nexys2 support expanded docs created tools directory	jt_eaton	5226d 14h	/
19	added serial_xmit module updated and added docs	jt_eaton	5233d 20h	/
18	added geda support files and docs	jt_eaton	5238d 18h	/
17	removed old doc files	jt_eaton	5240d 20h	/
16	added geda scripts and symbols/sch	jt_eaton	5240d 20h	/
15	added io_module with ps2 and uart added soc_mouse with uart and mouse interface fixed latch in mrisc	jt_eaton	5246d 23h	/
14	add web_uploads	jt_eaton	5257d 02h	/
13	updated for xilinx webpack 11.1	jt_eaton	5264d 17h	/
12	switched Makefile to use xilinx 11.1 ise removed timescale from synthesis files now use consist timescale header in all sims	jt_eaton	5265d 03h	/
11	moved bsdl files renamed ucf file	jt_eaton	5270d 23h	/
10	added impact_bat to generate svf files	jt_eaton	5271d 00h	/
9	updated build_cmp and cleaned up fpga script added more utility tools	jt_eaton	5273d 01h	/
8	fixed loop sim, now pick up ROM_WORDS from sw dir	jt_eaton	5275d 01h	/
7	changed loop to use subroutines fixed typo on variants name	jt_eaton	5276d 01h	/
6	added pic_micro from minirisc project with design to run code on a digilent Basys board	jt_eaton	5279d 21h	/
5	added testbench and generic clock model	jt_eaton	5281d 02h	/
4	added generic model for single ended generic pad	jt_eaton	5281d 02h	/
3	started bin and lib directories, added install instructions for ubuntu 9.04	jt_eaton	5281d 16h	/
2	added starting docs	jt_eaton	5283d 00h	/
1	The project and the structure was created	root	5283d 12h	/