URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 47

Rev	Log message	Author	Age	Path
47	removed old variant	jt_eaton	5090d 03h	/
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5090d 03h	/
45	added 6502 sims/software and synth	jt_eaton	5096d 23h	/
44	added new parts and sw for 6502	jt_eaton	5097d 02h	/
43	complete rework of states and sequencer added interrupts moved prog space and vectors to F space	jt_eaton	5107d 00h	/
42	removed old versions that used prog as C space	jt_eaton	5107d 00h	/
41	added kim-1 design and program now support Nexys2 sdram	jt_eaton	5125d 01h	/
40	removed test for deleted block	jt_eaton	5125d 01h	/
39	added io_probe to sims added boot rom into 6502 added T6502_control	jt_eaton	5133d 14h	/
38	fsm level removed	jt_eaton	5133d 14h	/
37	continued to clean up inst decodes to alu and move datapath out of sequencer removed latched alu_result, now uses raw	jt_eaton	5142d 21h	/
36	split out alu_ctrl block split out alu decode signals	jt_eaton	5143d 15h	/
35	added T6502 doc	jt_eaton	5144d 18h	/
34	removed BCD mode from T6502 started to convert design to use datapath logic for alu	jt_eaton	5149d 21h	/
33	removed unused block	jt_eaton	5149d 21h	/
32	renamed to T6502_state_fsm	jt_eaton	5150d 04h	/
31	split T6502_fsm out into smaller blocks	jt_eaton	5150d 18h	/
30	split out fsm code into seperate modules fixed bugs so that prog_test passes	jt_eaton	5153d 03h	/
29	removed old files	jt_eaton	5156d 02h	/
28	added T6502 processor added vga_char_ctrl	jt_eaton	5156d 02h	/