URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 55

Rev	Log message	Author	Age	Path
55	removed pre-rout and gates sims	jt_eaton	5188d 07h	/
54	now set up fpga targets from xml files	jt_eaton	5188d 08h	/
53	fixed check_fpgas	jt_eaton	5190d 22h	/
52	removed noworking sims and syn	jt_eaton	5190d 22h	/
51	removed old test	jt_eaton	5190d 22h	/
50	clean up from last checkin	jt_eaton	5190d 23h	/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5191d 02h	/
48	added support for covered code checking	jt_eaton	5213d 08h	/
47	removed old variant	jt_eaton	5227d 11h	/
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5227d 11h	/
45	added 6502 sims/software and synth	jt_eaton	5234d 07h	/
44	added new parts and sw for 6502	jt_eaton	5234d 10h	/
43	complete rework of states and sequencer added interrupts moved prog space and vectors to F space	jt_eaton	5244d 08h	/
42	removed old versions that used prog as C space	jt_eaton	5244d 09h	/
41	added kim-1 design and program now support Nexys2 sdram	jt_eaton	5262d 09h	/
40	removed test for deleted block	jt_eaton	5262d 10h	/
39	added io_probe to sims added boot rom into 6502 added T6502_control	jt_eaton	5270d 22h	/
38	fsm level removed	jt_eaton	5270d 22h	/
37	continued to clean up inst decodes to alu and move datapath out of sequencer removed latched alu_result, now uses raw	jt_eaton	5280d 05h	/
36	split out alu_ctrl block split out alu decode signals	jt_eaton	5280d 23h	/