URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 62

Rev	Log message	Author	Age	Path
62	fixed parameters from `defines	jt_eaton	5264d 14h	/
61	now generate dut files for coverage removed use of lndir	jt_eaton	5264d 16h	/
60	moved alu_logic into seperate component	jt_eaton	5265d 03h	/
59	added filelist.core to syn dirs to customize core	jt_eaton	5265d 03h	/
58	removed old Makefiles	jt_eaton	5265d 18h	/
57	Now generate all filelists from xml files	jt_eaton	5265d 19h	/
56	soc_builder now builds verilog from xml files	jt_eaton	5271d 03h	/
55	removed pre-rout and gates sims	jt_eaton	5273d 23h	/
54	now set up fpga targets from xml files	jt_eaton	5274d 00h	/
53	fixed check_fpgas	jt_eaton	5276d 14h	/
52	removed noworking sims and syn	jt_eaton	5276d 15h	/
51	removed old test	jt_eaton	5276d 15h	/
50	clean up from last checkin	jt_eaton	5276d 15h	/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5276d 18h	/
48	added support for covered code checking	jt_eaton	5299d 00h	/
47	removed old variant	jt_eaton	5313d 03h	/
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5313d 03h	/
45	added 6502 sims/software and synth	jt_eaton	5319d 23h	/
44	added new parts and sw for 6502	jt_eaton	5320d 02h	/
43	complete rework of states and sequencer added interrupts moved prog space and vectors to F space	jt_eaton	5330d 00h	/