URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 65

Rev	Log message	Author	Age	Path
65	added params.sim to sims updated install's	jt_eaton	5116d 07h	/
64	added support for Fedora 13	jt_eaton	5120d 06h	/
63	added install config for Ubuntu 10.10	jt_eaton	5120d 12h	/
62	fixed parameters from `defines	jt_eaton	5124d 05h	/
61	now generate dut files for coverage removed use of lndir	jt_eaton	5124d 06h	/
60	moved alu_logic into seperate component	jt_eaton	5124d 17h	/
59	added filelist.core to syn dirs to customize core	jt_eaton	5124d 17h	/
58	removed old Makefiles	jt_eaton	5125d 08h	/
57	Now generate all filelists from xml files	jt_eaton	5125d 09h	/
56	soc_builder now builds verilog from xml files	jt_eaton	5130d 17h	/
55	removed pre-rout and gates sims	jt_eaton	5133d 14h	/
54	now set up fpga targets from xml files	jt_eaton	5133d 15h	/
53	fixed check_fpgas	jt_eaton	5136d 04h	/
52	removed noworking sims and syn	jt_eaton	5136d 05h	/
51	removed old test	jt_eaton	5136d 05h	/
50	clean up from last checkin	jt_eaton	5136d 05h	/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5136d 08h	/
48	added support for covered code checking	jt_eaton	5158d 14h	/
47	removed old variant	jt_eaton	5172d 17h	/
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5172d 18h	/