URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 70

Rev	Log message	Author	Age	Path
70	ignore work	jt_eaton	5162d 01h	/
69	added work dir	jt_eaton	5162d 01h	/
68	moved to seperate components	jt_eaton	5165d 00h	/
67	updated installs	jt_eaton	5165d 01h	/
66	converted sims to use parameters added msp and 6502 software installs	jt_eaton	5166d 00h	/
65	added params.sim to sims updated install's	jt_eaton	5171d 00h	/
64	added support for Fedora 13	jt_eaton	5174d 23h	/
63	added install config for Ubuntu 10.10	jt_eaton	5175d 06h	/
62	fixed parameters from `defines	jt_eaton	5178d 22h	/
61	now generate dut files for coverage removed use of lndir	jt_eaton	5178d 23h	/
60	moved alu_logic into seperate component	jt_eaton	5179d 11h	/
59	added filelist.core to syn dirs to customize core	jt_eaton	5179d 11h	/
58	removed old Makefiles	jt_eaton	5180d 02h	/
57	Now generate all filelists from xml files	jt_eaton	5180d 02h	/
56	soc_builder now builds verilog from xml files	jt_eaton	5185d 11h	/
55	removed pre-rout and gates sims	jt_eaton	5188d 07h	/
54	now set up fpga targets from xml files	jt_eaton	5188d 08h	/
53	fixed check_fpgas	jt_eaton	5190d 21h	/
52	removed noworking sims and syn	jt_eaton	5190d 22h	/
51	removed old test	jt_eaton	5190d 22h	/