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Rev Log message Author Age Path
71 ignore anything in work jt_eaton 5157d 13h /
70 ignore work jt_eaton 5157d 13h /
69 added work dir jt_eaton 5157d 13h /
68 moved to seperate components jt_eaton 5160d 12h /
67 updated installs jt_eaton 5160d 13h /
66 converted sims to use parameters
added msp and 6502 software installs
jt_eaton 5161d 12h /
65 added params.sim to sims
updated install's
jt_eaton 5166d 13h /
64 added support for Fedora 13 jt_eaton 5170d 11h /
63 added install config for Ubuntu 10.10 jt_eaton 5170d 18h /
62 fixed parameters from `defines jt_eaton 5174d 10h /
61 now generate dut files for coverage
removed use of lndir
jt_eaton 5174d 12h /
60 moved alu_logic into seperate component jt_eaton 5174d 23h /
59 added filelist.core to syn dirs to customize core jt_eaton 5174d 23h /
58 removed old Makefiles jt_eaton 5175d 14h /
57 Now generate all filelists from xml files jt_eaton 5175d 14h /
56 soc_builder now builds verilog from xml files jt_eaton 5180d 23h /
55 removed pre-rout and gates sims jt_eaton 5183d 19h /
54 now set up fpga targets from xml files jt_eaton 5183d 20h /
53 fixed check_fpgas jt_eaton 5186d 10h /
52 removed noworking sims and syn jt_eaton 5186d 10h /

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