URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 72

Rev	Log message	Author	Age	Path
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	5047d 15h	/
71	ignore anything in work	jt_eaton	5054d 08h	/
70	ignore work	jt_eaton	5054d 08h	/
69	added work dir	jt_eaton	5054d 08h	/
68	moved to seperate components	jt_eaton	5057d 08h	/
67	updated installs	jt_eaton	5057d 08h	/
66	converted sims to use parameters added msp and 6502 software installs	jt_eaton	5058d 07h	/
65	added params.sim to sims updated install's	jt_eaton	5063d 08h	/
64	added support for Fedora 13	jt_eaton	5067d 06h	/
63	added install config for Ubuntu 10.10	jt_eaton	5067d 13h	/
62	fixed parameters from `defines	jt_eaton	5071d 05h	/
61	now generate dut files for coverage removed use of lndir	jt_eaton	5071d 07h	/
60	moved alu_logic into seperate component	jt_eaton	5071d 18h	/
59	added filelist.core to syn dirs to customize core	jt_eaton	5071d 18h	/
58	removed old Makefiles	jt_eaton	5072d 09h	/
57	Now generate all filelists from xml files	jt_eaton	5072d 10h	/
56	soc_builder now builds verilog from xml files	jt_eaton	5077d 18h	/
55	removed pre-rout and gates sims	jt_eaton	5080d 14h	/
54	now set up fpga targets from xml files	jt_eaton	5080d 15h	/
53	fixed check_fpgas	jt_eaton	5083d 05h	/