URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 79

Rev	Log message	Author	Age	Path
79	removed unsupported code	jt_eaton	4998d 17h	/
78	removed unsupported fpga	jt_eaton	4998d 17h	/
77	now generate syn and cov Makefiles leave log and out files in sim/run directory	jt_eaton	4998d 17h	/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	5000d 22h	/
75	added linting using verilator	jt_eaton	5004d 15h	/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5009d 20h	/
73	removed dup png files	jt_eaton	5017d 20h	/
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	5017d 22h	/
71	ignore anything in work	jt_eaton	5024d 14h	/
70	ignore work	jt_eaton	5024d 14h	/
69	added work dir	jt_eaton	5024d 14h	/
68	moved to seperate components	jt_eaton	5027d 14h	/
67	updated installs	jt_eaton	5027d 14h	/
66	converted sims to use parameters added msp and 6502 software installs	jt_eaton	5028d 14h	/
65	added params.sim to sims updated install's	jt_eaton	5033d 14h	/
64	added support for Fedora 13	jt_eaton	5037d 13h	/
63	added install config for Ubuntu 10.10	jt_eaton	5037d 20h	/
62	fixed parameters from `defines	jt_eaton	5041d 12h	/
61	now generate dut files for coverage removed use of lndir	jt_eaton	5041d 13h	/
60	moved alu_logic into seperate component	jt_eaton	5042d 00h	/