URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 89

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Rev	Log message	Author	Age	Path
89	removed unneeded debug directories	jt_eaton	4965d 06h	/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4965d 06h	/
87	removed prebuilt geda schematics and symbols	jt_eaton	4975d 23h	/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4983d 20h	/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4990d 19h	/
84	removed unneeded files	jt_eaton	5041d 00h	/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	5041d 05h	/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	5055d 23h	/
81	morphing xml files to use 1685 removed log directories	jt_eaton	5077d 05h	/
80	now generate all sims and syns param and filelists for xml	jt_eaton	5106d 20h	/
79	removed unsupported code	jt_eaton	5113d 01h	/
78	removed unsupported fpga	jt_eaton	5113d 01h	/
77	now generate syn and cov Makefiles leave log and out files in sim/run directory	jt_eaton	5113d 01h	/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	5115d 07h	/
75	added linting using verilator	jt_eaton	5118d 23h	/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5124d 04h	/
73	removed dup png files	jt_eaton	5132d 04h	/
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	5132d 06h	/
71	ignore anything in work	jt_eaton	5138d 22h	/
70	ignore work	jt_eaton	5138d 23h	/

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Subversion Repositories socgen

[/] - Rev 89

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