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Subversion Repositories spacewiresystemc

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Rev Log message Author Age Path
26 Adding write axi and updating files. redbear 2562d 15h /
25 Updating redbear 2562d 15h /
24 Removing altera quartus 16.0 redbear 2562d 15h /
23 FPGA verilog and corrections. redbear 2591d 15h /
22 Adding files work to altera fpga DE0 NANO SOC. redbear 2591d 15h /
21 Vpi data rx. redbear 2612d 14h /
20 SystemC minor correction. redbear 2612d 14h /
19 RX and TX correct. redbear 2612d 14h /
18 FSM minor correction redbear 2619d 14h /
17 TX correction FCT reaceive and TX data transfer. redbear 2619d 14h /
16 Adding TX_WRITE to go down after detect first edge posedge tx_ready. redbear 2619d 14h /
15 Tx with FCT with partial correction. redbear 2647d 15h /
14 New version of Receiver. redbear 2647d 15h /
13 upating files. redbear 2674d 15h /
12 update files and SystemC. redbear 2696d 15h /
11 Adding shared object. redbear 2706d 16h /
10 Update tx verilog rx systemc test. redbear 2706d 16h /
9 Update shared object and Graphical interface. redbear 2706d 16h /
8 EOPDATA is functional. redbear 2706d 16h /
7 Updating testbench file using correcting signals VPI. redbear 2711d 17h /

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