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Rev Log message Author Age Path
44 Transmitter Wishbone bus cycle decoder. gedra 7449d 09h /
43 This commit was manufactured by cvs2svn to create tag 'rx_beta_1'. 7450d 11h /
42 Fixed bug with lock event generation. gedra 7450d 11h /
41 Test bench update. gedra 7450d 11h /
40 Improved test bench. gedra 7451d 12h /
39 Bug-fix. gedra 7451d 12h /
38 Signal renaming and bug fix. gedra 7465d 12h /
37 Converted to numeric_std and fixed a few bugs. gedra 7466d 14h /
36 Top level entity for receiver. gedra 7466d 14h /
35 Top level test bench for receiver. NB! Not complete. gedra 7466d 14h /
34 Converter to numeric_std and added hex functions gedra 7466d 14h /
33 Minor update. gedra 7466d 14h /
32 Wishbone bus utilities. gedra 7468d 09h /
31 Added data output. gedra 7468d 09h /
30 Added Wishbone bus cycle decoder. gedra 7469d 10h /
29 Wishbone bus cycle decoder. gedra 7469d 10h /
28 Delint'ed and changed name of architecture. gedra 7473d 18h /
27 Alternate dual port memory implementation for Altera FPGA's. gedra 7474d 09h /
26 Fixed a few bugs. gedra 7476d 09h /
25 Changed status reg. declaration gedra 7476d 09h /

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