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25 CTRL register bit fields changed, VATS testing support added. simons 7691d 02h /
24 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7942d 04h /
23 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7942d 04h /
22 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7942d 04h /
21 Byte selects changed. simons 7942d 04h /
20 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7943d 08h /
19 Errors fixed. simons 7943d 08h /
18 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7946d 05h /
17 Define mess fixed. simons 7946d 05h /
16 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7946d 09h /
15 Defines set in order. simons 7946d 09h /
14 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7947d 02h /
13 8-bit WB access enabled. simons 7947d 02h /
12 Error fixed. simons 7967d 10h /
11 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7985d 09h /
10 Slave select signal generation bug fixed, default case added when reading registers, to avoid latches. simons 7985d 09h /
9 Support for 128 bits character length added. Zero value divider bug fixed. simons 8026d 03h /
8 Automatic slave select signal generation added. simons 8046d 04h /
7 Support for 64 bit caharacter len added. simons 8134d 16h /
6 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8302d 19h /

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