OpenCores
URL https://opencores.org/ocsvn/spi/spi/trunk

Subversion Repositories spi

[/] - Rev 25

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
25 CTRL register bit fields changed, VATS testing support added. simons 7553d 11h /
24 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7804d 13h /
23 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7804d 13h /
22 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7804d 13h /
21 Byte selects changed. simons 7804d 13h /
20 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7805d 18h /
19 Errors fixed. simons 7805d 18h /
18 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7808d 14h /
17 Define mess fixed. simons 7808d 14h /
16 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7808d 18h /
15 Defines set in order. simons 7808d 18h /
14 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7809d 11h /
13 8-bit WB access enabled. simons 7809d 11h /
12 Error fixed. simons 7829d 19h /
11 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7847d 18h /
10 Slave select signal generation bug fixed, default case added when reading registers, to avoid latches. simons 7847d 18h /
9 Support for 128 bits character length added. Zero value divider bug fixed. simons 7888d 12h /
8 Automatic slave select signal generation added. simons 7908d 13h /
7 Support for 64 bit caharacter len added. simons 7997d 01h /
6 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8165d 04h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.