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Rev Log message Author Age Path
56 source code kindly provided by Michael Libeskind arniml 6746d 22h /
55 document rev. 3.2 arniml 6812d 17h /
54 revision 3.2:
+ detailed description of generic parameters
+ formatting and typos fixed
arniml 6812d 17h /
53 fix last set number arniml 6812d 17h /
52 fix typo arniml 6812d 18h /
51 revision 3.1:
+ formatting corrected
arniml 7146d 23h /
50 document rev. 3.1 arniml 7146d 23h /
49 add doc directory to project structure arniml 7148d 13h /
48 add ram_loader and related testbench arniml 7148d 13h /
47 schematic revision C arniml 7148d 13h /
46 document rev. 3.0 arniml 7148d 13h /
45 revision 3.0:
+ added detached output
+ describe interfacing on data port
+ several improvements
arniml 7148d 13h /
44 add detached output arniml 7148d 13h /
43 add new testbench for ram_loader arniml 7152d 16h /
42 initial check-in arniml 7152d 16h /
41 rework for detached_i information arniml 7152d 17h /
40 add new port detached_o arniml 7155d 13h /
39 describe sets
-> prepared for release of version 2.0, rev. B
arniml 7180d 16h /
38 invert level of set_sel input arniml 7184d 14h /
37 make verbosity level switchable arniml 7184d 14h /

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