OpenCores
URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] - Rev 10

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
10 v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register).
Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise.		 jdoin 4906d 10h /
9 Updated verification data. jdoin 4909d 23h /
8 Updated Documentation jdoin 4909d 23h /
7 Updated code comments in VHDL files, added readme.txt files, updated work-in-progress version of the .doc core specification manual. jdoin 4910d 13h /
6 v1.10.0075: Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.		 jdoin 4912d 09h /
5 Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.		 jdoin 4912d 10h /
4 v0.97.0068 - streamlined resets and clock enables to reduce area
v0.97.0075 - redesigned parallel interfaces, with pipelined data transport for async clock domains
v0.97.0083 - fixed bug "CPHA effect": redesigned SCK output circuit
v0.97.0086 - removed master MISO input register: got 33MHz.		 jdoin 4937d 10h /
3 - fixed fsm async glitches at state changes
- changed async clears to sync resets
- improved idle state logic for parallel interface
- added cross-clock register buffers
- exposed internal state and nets for debug		 jdoin 4946d 08h /
2 v0.95.0050 - Master/Slave loopback verified at 25MHz. jdoin 4954d 14h /
1 The project and the structure was created root 4968d 08h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.