URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] - Rev 6

Rev	Log message	Author	Age	Path
6	v1.10.0075: Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing. Added SPI line clock divider from high-speed system clock. Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies. Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.	jdoin	4869d 21h	/
5	Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing. Added SPI line clock divider from high-speed system clock. Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies. Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.	jdoin	4869d 21h	/
4	v0.97.0068 - streamlined resets and clock enables to reduce area v0.97.0075 - redesigned parallel interfaces, with pipelined data transport for async clock domains v0.97.0083 - fixed bug "CPHA effect": redesigned SCK output circuit v0.97.0086 - removed master MISO input register: got 33MHz.	jdoin	4894d 21h	/
3	- fixed fsm async glitches at state changes - changed async clears to sync resets - improved idle state logic for parallel interface - added cross-clock register buffers - exposed internal state and nets for debug	jdoin	4903d 19h	/
2	v0.95.0050 - Master/Slave loopback verified at 25MHz.	jdoin	4912d 01h	/
1	The project and the structure was created	root	4925d 20h	/