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Rev Log message Author Age Path
14 - Modified large FIFO to remove "full" signal and store only N-1 words
- changed small FIFO to use memory instance instead of registers
- changed sequence generator to enable more complex tests
- changed sd_mirror to use combinatorial assign output
ghutchis 5425d 02h /
13 Fixed FIFO Full condition for large fifo, added separate
tests to example bridge
ghutchis 5428d 13h /
12 Added absolute priority arbitration to ring to avoid
having two ring taps transmit at same time
ghutchis 5429d 13h /
11 Updated bridge example to fix a number of small bugs.
First packet now exits bridge from all ports.
ghutchis 5430d 11h /
10 Fixed "locked" variable in rrslow ghutchis 5430d 16h /
9 Added rx_gigmac, additional debug work on concentrator & fib ghutchis 5430d 16h /
8 Added compiling version of bridge example ghutchis 5432d 04h /
7 Added rrslow ghutchis 5434d 08h /
6 Modified "B" output buffer for full-rate operation ghutchis 5436d 16h /
5 Added new component for port ring ghutchis 5437d 08h /
4 Added example directory with basic bridge ghutchis 5438d 03h /
3 Added small/synchronizer FIFO, along with minimal testbench ghutchis 5439d 02h /
2 Initial commit of directory structure and basic components ghutchis 5443d 11h /
1 The project and the structure was created root 5451d 03h /

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