OpenCores
URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] - Rev 22

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
22 Created separate module-level environments for fifo_b
and scoreboard. Added some documentation on the
example bridge, including a PDF preso giving a basic
introduction to ethernet.
ghutchis 5253d 23h /
21 Changed rrslow to rrmux, updated descriptions, changed
bridge mux to fast arb
ghutchis 5255d 01h /
20 Added fast arb mode ghutchis 5255d 03h /
19 Fixed several minor bugs in scoreboard, adjusted usage width in sd_fifo_b,
and updated component documentation.
ghutchis 5255d 15h /
18 Added scoreboard and scoreboard testbench ghutchis 5255d 19h /
17 Added component descriptions ghutchis 5256d 04h /
16 Changed fifo head/tail to have separate usage counters for producer and consumer
side.

Fixed bug in port_ring_tap where it jumped to non-existent state.

Changed default dump mode for icarus to lxt.
ghutchis 5256d 16h /
15 Fixed FIB lookup multicast -- multicast packets were being
repeatedly sent from lookup
ghutchis 5256d 20h /
14 - Modified large FIFO to remove "full" signal and store only N-1 words
- changed small FIFO to use memory instance instead of registers
- changed sequence generator to enable more complex tests
- changed sd_mirror to use combinatorial assign output
ghutchis 5258d 14h /
13 Fixed FIFO Full condition for large fifo, added separate
tests to example bridge
ghutchis 5262d 01h /
12 Added absolute priority arbitration to ring to avoid
having two ring taps transmit at same time
ghutchis 5263d 00h /
11 Updated bridge example to fix a number of small bugs.
First packet now exits bridge from all ports.
ghutchis 5263d 23h /
10 Fixed "locked" variable in rrslow ghutchis 5264d 04h /
9 Added rx_gigmac, additional debug work on concentrator & fib ghutchis 5264d 04h /
8 Added compiling version of bridge example ghutchis 5265d 16h /
7 Added rrslow ghutchis 5267d 19h /
6 Modified "B" output buffer for full-rate operation ghutchis 5270d 04h /
5 Added new component for port ring ghutchis 5270d 20h /
4 Added example directory with basic bridge ghutchis 5271d 14h /
3 Added small/synchronizer FIFO, along with minimal testbench ghutchis 5272d 14h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.