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Rev	Log message	Author	Age	Path
55	simplified regf_status interface	samg	8375d 09h	/
54	fixed case statement, sensitivity list	samg	8378d 00h	/
53	comment spelling fix	samg	8378d 00h	/
52	minor expression rewrite in 4th stage	samg	8383d 10h	/
51	Rewrote verilog for write enable signals for different destinations in the last stage. The code is much easier to read and more liner to follow.	samg	8384d 08h	/
50	fixed sensitivity list error in last pipeline stage	samg	8384d 20h	/
49	changed run script name and added instructions	samg	8384d 20h	/
48	fixed neg edge event trigger	samg	8384d 20h	/
47	changed prefix from ~\| to ! (same thing)	samg	8384d 20h	/
46	vcd dumpvar captures all levels	samg	8387d 07h	/
45	Fixed bug in 16 bit data swap instruction. The instructions were making the regf status module look at reg 0 even though reg 0 didn't have anything to do with the purpose of the instruction. Made reg b addr field mirror reg a field. This error caused unecessary stalls. Performance increase caused by calling instruction correctly and not causing stalls from mal-formed instructions.	samg	8387d 07h	/
44	- Removed #1 delay (was originally put in for debug) - Stall signal forced low during pipeline flush. (No effect on functionality but it is easier to look at the waveforms during debug)	samg	8387d 07h	/
43	integrated common rams into processor	samg	8411d 01h	/
42	minor header correction	samg	8411d 01h	/
41	common rams	samg	8411d 01h	/
40	added header and parameter restructure	samg	8411d 02h	/
39	added header and restructured parameters	samg	8411d 02h	/
38	minor header fix	samg	8411d 02h	/
37	added header and modified parameter structure	samg	8411d 02h	/
36	integrated common memories	samg	8411d 02h	/

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[/] - Rev 55

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