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Rev Log message Author Age Path
19 moved elements to separate design unit tb_elems arniml 6761d 13h /
18 initial check-in arniml 6761d 13h /
17 remove direct specification of cpu type arniml 6762d 12h /
16 enabled t420 support arniml 6762d 12h /
15 initial check-in arniml 6762d 12h /
14 t420 hierarchies added arniml 6762d 12h /
13 hand-down clock divider option arniml 6769d 08h /
12 fix sensitivity list arniml 6770d 08h /
11 renamed to rtl arniml 6770d 09h /
10 renamed t400_por configuration to rtl arniml 6770d 09h /
9 initial check-in arniml 6770d 09h /
8 phi1_en_q is dedicated enable for PHI1 clock to suppress glitches on sk_o arniml 6770d 21h /
7 remove delta cycle filter on sk_s arniml 6770d 21h /
6 initial check-in arniml 6770d 21h /
5 initial check-in arniml 6771d 08h /
4 remove superfluous testbench arniml 6771d 08h /
3 This commit was manufactured by cvs2svn to create tag 'LOC_CVS_0_1'. 6771d 09h /
2 import from local CVS repository, LOC_CVS_0_1 arniml 6771d 09h /
1 Standard project directories initialized by cvs2svn. 6771d 09h /

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