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Rev Log message Author Age Path
22 finish test arniml 6760d 15h /
21 include t420 system and testbench arniml 6760d 16h /
20 initial check-in arniml 6760d 16h /
19 moved elements to separate design unit tb_elems arniml 6760d 16h /
18 initial check-in arniml 6760d 16h /
17 remove direct specification of cpu type arniml 6761d 16h /
16 enabled t420 support arniml 6761d 16h /
15 initial check-in arniml 6761d 16h /
14 t420 hierarchies added arniml 6761d 16h /
13 hand-down clock divider option arniml 6768d 12h /
12 fix sensitivity list arniml 6769d 12h /
11 renamed to rtl arniml 6769d 13h /
10 renamed t400_por configuration to rtl arniml 6769d 13h /
9 initial check-in arniml 6769d 13h /
8 phi1_en_q is dedicated enable for PHI1 clock to suppress glitches on sk_o arniml 6770d 01h /
7 remove delta cycle filter on sk_s arniml 6770d 01h /
6 initial check-in arniml 6770d 01h /
5 initial check-in arniml 6770d 12h /
4 remove superfluous testbench arniml 6770d 12h /
3 This commit was manufactured by cvs2svn to create tag 'LOC_CVS_0_1'. 6770d 12h /

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