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Rev Log message Author Age Path
25 fix wrong aisc commands arniml 6767d 20h /
24 finalize test arniml 6767d 21h /
23 finalize test arniml 6768d 12h /
22 finish test arniml 6768d 20h /
21 include t420 system and testbench arniml 6768d 21h /
20 initial check-in arniml 6768d 21h /
19 moved elements to separate design unit tb_elems arniml 6768d 22h /
18 initial check-in arniml 6768d 22h /
17 remove direct specification of cpu type arniml 6769d 21h /
16 enabled t420 support arniml 6769d 21h /
15 initial check-in arniml 6769d 21h /
14 t420 hierarchies added arniml 6769d 21h /
13 hand-down clock divider option arniml 6776d 17h /
12 fix sensitivity list arniml 6777d 17h /
11 renamed to rtl arniml 6777d 18h /
10 renamed t400_por configuration to rtl arniml 6777d 18h /
9 initial check-in arniml 6777d 18h /
8 phi1_en_q is dedicated enable for PHI1 clock to suppress glitches on sk_o arniml 6778d 06h /
7 remove delta cycle filter on sk_s arniml 6778d 06h /
6 initial check-in arniml 6778d 07h /

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